january 2004 dsc-3624/09 1 ?2004 integrated device technology, inc. features 256k x 16 advanced high-speed cmos static ram jedec center power / gnd pinout for reduced noise. equal access and cycle times ? commercial and industrial: 10/12/15ns one chip select plus one output enable pin bidirectional data inputs and outputs directly lvttl-compatible low power consumption via chip deselect upper and lower byte enable pins single 3.3v power supply available in 44-pin, 400 mil plastic soj package and a 44- pin, 400 mil tsop type ii package and a 48 ball grid array, 9mm x 9mm package. description the idt71v416 is a 4,194,304-bit high-speed static ram organized as 256k x 16. it is fabricated using idt?s high-perfomance, high-reliability cmos technology. this state-of-the-art technology, combined with inno- vative circuit design techniques, provides a cost-effective solution for high- speed memory needs. the idt71v416 has an output enable pin which operates as fast as 5ns, with address access times as fast as 10ns. all bidirectional inputs and outputs of the idt71v416 are lvttl-compatible and operation is from a single 3.3v supply. fully static asynchronous circuitry is used, requiring no clocks or refresh for operation. the idt71v416 is packaged in a 44-pin, 400 mil plastic soj and a 44-pin, 400 mil tsop type ii package and a 48 ball grid array, 9mm x 9mm package. functional block diagram output enable buffer address buffers chip select buffer write enable buffer byte enable buffers oe a0 - a17 row / column decoders cs we bhe ble 4,194,304-bit memory array sense amps and write drivers 16 high byte output buffer high byte write buffer low byte write buffer low byte output buffer 8 8 8 8 8 8 8 8 i/o 15 i/o 8 i/o 7 i/o 0 3624 drw 01 3.3v cmos static ram 4 meg (256k x 16-bit) idt71v416s IDT71V416L
6.42 2 idt71v416s, IDT71V416L, 3.3v cmos static ram 4 meg (256k x 16-bit) commercial a nd industrial temperature ranges *pin 28 can either be a nc or connected to vss top view pin configurations - soj/tsop pin descriptions soj capacitance (t a = +25c, f = 1.0mhz) note: 1. this parameter is guaranteed by device characterization, but not production tested. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 i/o 7 a9 a8 a7 a6 a5 we i/o 6 i/o 5 i/o 4 v ss v dd i/o 3 i/o 2 i/o 1 i/o 0 cs a4 a3 a2 a1 a0 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 a16 a15 oe bhe ble i/o 15 i/o 14 i/o 13 i/o 12 v ss v dd i/o 11 i/o 10 i/o 9 i/o 8 a14 a13 a12 a11 a10 a17 nc* so44-1 so44-2 3624 drw 02 a 0 - a 17 address inputs input cs chip select input we write enable input oe output enable input bhe high byte enable input ble low byte enable input i/o 0 - i/o 15 data input/output i/o v dd 3.3v power pwr v ss ground gnd 3624 tbl 01 symbol parameter (1) conditions max. unit c in input capacitance v in = 3dv 7 pf c i/o i/o capacitance v out = 3dv 8 pf 3624 tbl 02 123456 a ble oe a 0 a 1 a 2 nc bi/o 0 bhe a 3 a 4 cs i/o 8 ci/o 1 i/o 2 a 5 a 6 i/o 10 i/o 9 dv ss i/o 3 a 17 a 7 i/o 11 v dd ev dd i/o 4 nc a 16 i/o 12 v ss fi/o 6 i/o 5 a 14 a 15 i/o 13 i/o 14 gi/o 7 nc a 12 a 13 we i/o 15 hnc a 8 a 9 a 10 a 11 nc 3624 tbl 1 1 pin configurations - 48 bga 48 bga capacitance (t a = +25c, f = 1.0mhz) symbol parameter (1) conditions max. unit c in input capacitance v in = 3dv 6 pf c i/o i/o capacitance v out = 3dv 7 pf 3624 tb l 02b
6.42 idt71v416s, IDT71V416L, 3.3v cmos static ram 4 meg (256k x 16-bit) commercial a nd industrial temperature ranges 3 absolute maximum ratings (1) recommended operating temperature and supply voltage recommended dc operating conditions note: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. notes: 1. vih (max.) = vdd+2v for pulse width less than 5ns, once per cycle. 2. vil (min.) = ?2v for pulse width less than 5ns, once per cycle. truth table (1) note: 1. h = v ih , l = v il , x = don't care. symbol rating value unit v dd supply voltage relative to v ss -0.5 to +4.6 v v in, v out terminal voltage relative to v ss -0.5 to v dd +0.5 v t bias temperature under bias -55 to +125 o c t stg storage temperature -55 to +125 o c p t power dissipation 1 w i out dc output current 50 ma 3624 tbl 04 grade temperature v ss v dd commercial 0 o c to +70 o c0vsee below industrial ?40 o c to +85 o c0vsee below 3624 tbl 05 symbol parameter min. typ. max. unit v dd supply voltage 3.0 3.3 3.6 v v ss ground 0 0 0 v v ih input high voltage 2.0 ____ v dd +0.3 (1 ) v v il input low voltage -0.3 (2) ____ 0.8 v 3624 tbl 06 cs oe we ble bhe i/o 0- i/o 7 i/o 8- i/o 15 function h x x x x high-z high-z deselected - standby llhlhdata out high-z low byte read l l h h l high-z data out high byte read llhlldata out data out word read lxlll data in data in word write lxllh data in high-z low byte write l x l h l high-z data in high byte write l h h x x high-z high-z outputs disabled l x x h h high-z high-z outputs disabled 3624 tbl 03
6.42 4 idt71v416s, IDT71V416L, 3.3v cmos static ram 4 meg (256k x 16-bit) commercial a nd industrial temperature ranges ac test conditions ac test loads figure 3. output capacitive derating figure 1. ac test load figure 2. ac test load (for t clz , t olz , t chz , t ohz , t ow , and t whz ) *including jig and scope capacitance. input pulse levels input rise/fall times input timing reference levels output reference levels ac test load gnd to 3.0v 1.5ns 1.5v 1.5v figures 1,2 and 3 3624 tbl 09 +1.5v 50 ? i/o z 0 =50 ? 3624 drw 03 30pf 3624 drw 04 320 ? 350 ? 5pf* data out 3.3v idt71v416s/71v416l 1 2 3 4 5 6 7 20 40 60 80 100 120 140 160 180 200 ? t aa, t acs (typical, ns) capacitance (pf) 8 3624 drw 05 ? ? ? ? ? ? ? dc electrical characteristics (v dd = min. to max., commercial and industrial temperature ranges) dc electrical characteristics (1, 2, 3) (v dd = min. to max., v lc = 0.2v, v hc = v dd ? 0.2v) notes: 1. all values are maximum guaranteed values. 2. all inputs switch between 0.2v (low) and v dd -0.2v (high). 3. power specifications are preliminary. 4. fmax = 1/t rc (all address inputs are cycling at f max ); f = 0 means no address input lines are changing. 5. standard power 10ns (s10) speed grade only. symbol parameter 71v416s/l10 71v416s/l12 71v416s/l15 unit com'l. ind. (5 ) com'l. ind. com'l. ind. i cc dy namic operating current cs < v lc , outputs open, v dd = max., f = f max (4 ) s 200 200 180 180 170 170 ma l 180 ? 170 170 160 160 i sb dynamic standby power supply current cs > v hc , outputs open, v dd = max., f = f max (4 ) s707060605050 ma l 50 ? 45 45 40 40 i sb1 full standby pow er supply current (static) cs > v hc , outputs open, v dd = max., f = 0 (4 ) s202020202020 ma l 10 ? 10 10 10 10 3624 tbl 08 symbol parameter test conditions idt71v416 unit min. max. |i li | input leakage current v cc = max., v in = v ss to v dd ___ 5a |i lo | output leakage current v dd = max., cs = v ih , v out = v ss to v dd ___ 5a v ol output low voltage i ol = 8ma, v dd = min. ___ 0.4 v v oh output high voltage i oh = -4ma, v dd = min. 2.4 ___ v 3624 tbl 07
6.42 idt71v416s, IDT71V416L, 3.3v cmos static ram 4 meg (256k x 16-bit) commercial a nd industrial temperature ranges 5 71v416s/l10 (2 ) 71v416s/l12 71v416s/l15 symbol parameter min. max. min. max. min. max. unit read cycle t rc read cycle time 10 ____ 12 ____ 15 ____ ns t aa address access time ____ 10 ____ 12 ____ 15 ns t acs chip select access time ____ 10 ____ 12 ____ 15 ns t cl z (1) chip select low to output in low-z 4 ____ 4 ____ 4 ____ ns t chz (1) chip select high to output in high-z ____ 5 ____ 6 ____ 7ns t oe output enable low to output valid ____ 5 ____ 6 ____ 7ns t olz (1 ) output enable low to output in low-z 0 ____ 0 ____ 0 ____ ns t ohz (1) output enable high to output in high-z ____ 5 ____ 6 ____ 7ns t oh output hold from address change 4 ____ 4 ____ 4 ____ ns t be b yte enable low to output valid ____ 5 ____ 6 ____ 7ns t blz (1) byte enable low to output in low-z 0 ____ 0 ____ 0 ____ ns t bhz (1) byte enable high to output in high-z ____ 5 ____ 6 ____ 7ns write cycle t wc write cycle time 10 ____ 12 ____ 15 ____ ns t aw address valid to end of write 8 ____ 8 ____ 10 ____ ns t cw chip select low to end of write 8 ____ 8 ____ 10 ____ ns t bw byte enable low to end of write 8 ____ 8 ____ 10 ____ ns t as address set-up time 0 ____ 0 ____ 0 ____ ns t wr address hold from end of write 0 ____ 0 ____ 0 ____ ns t wp write pulse width 8 ____ 8 ____ 10 ____ ns t dw data valid to end of write 5 ____ 6 ____ 7 ____ ns t dh data hold time 0 ____ 0 ____ 0 ____ ns t ow (1) write enable high to output in low-z 3 ____ 3 ____ 3 ____ ns t whz (1) write enable low to output in high-z ____ 6 ____ 7 ____ 7ns 3624 tbl 10 timing waveform of read cycle no. 1 (1,2,3) ac electrical characteristics (v dd = min. to max., commercial and industrial temperature ranges) note: 1. this parameter is guaranteed with the ac load (figure 2) by device characterization, but is not production tested. 2. low power 10ns (l10) speed 0oc to +70oc temperature range only. data out address 3624 drw 06 t rc t aa t oh data out valid previous data out valid t oh notes: 1. we is high for read cycle. 2. device is continuously selected, cs is low. 3. oe , bhe , and ble are low.
6.42 6 idt71v416s, IDT71V416L, 3.3v cmos static ram 4 meg (256k x 16-bit) commercial a nd industrial temperature ranges address oe cs data out 3624 drw 07 (3) data valid t aa t rc t oe t olz bhe , ble (3) t acs (3) t blz t clz (2) t be (2) t oh t ohz (3) t chz (3) t bhz (3) out timing waveform of read cycle no. 2 (1) notes: 1. a write occurs during the overlap of a low cs , low bhe or ble , and a low we . 2. oe is continuously high. if during a we controlled write cycle oe is low, t wp must be greater than or equal to t whz + t dw to allow the i/o drivers to turn off and data to be placed on the bus for the required t dw . if oe is high during a we controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified t wp . 3. during this period, i/o pins are in the output state, and input signals must not be applied. 4. if the cs low or bhe and ble low transition occurs simultaneously with or after the we low transition, the outputs remain in a high-impedance state. 5. transition is measured 200mv from steady state. timing waveform of write cycle no. 1 ( we controlled timing) (1,2,4) notes: 1. we is high for read cycle. 2. address must be valid prior to or coincident with the later of cs , bhe , or ble transition low; otherwise t aa is the limiting parameter. 3. transition is measured 200mv from steady state. address cs data in 3624 drw 0 (5) (5) (5) data in valid t wc t as t whz (2) t cw t chz t ow t wr we t aw data out t dw t dh previous data valid data valid bhe , ble t bw t wp (5) t bhz (3)
6.42 idt71v416s, IDT71V416L, 3.3v cmos static ram 4 meg (256k x 16-bit) commercial a nd industrial temperature ranges 7 timing waveform of write cycle no. 2 ( cs controlled timing) (1,3) notes: 1. a write occurs during the overlap of a low cs , low bhe or ble , and a low we . 2. during this period, i/o pins are in the output state, and input signals must not be applied. 3. if the cs low or bhe and ble low transition occurs simultaneously with or after the we low transition, the outputs remain in a high-impedance state. timing waveform of write cycle no. 3 ( bhe , ble controlled timing) (1,3) address cs data in 3624 drw 09 data in valid t wc t as (2) t cw t wr we t aw data out t dw t dh bhe, ble t bw t wp address cs data in 3624 drw 10 data in valid t wc t as (2) t cw t wr we t aw data out t dw t dh bhe, ble t bw t wp
6.42 8 idt71v416s, IDT71V416L, 3.3v cmos static ram 4 meg (256k x 16-bit) commercial a nd industrial temperature ranges x power xx speed xxx package x process/ temperature range blank i commercial (0c to +70c) industrial (-40c to +85c) y ph be 44-pin, 400-mil soj (so44-1) 44-pin tsop type ii (so44-2) 48 ball grid array 10* 12 15 71v416 device type idt speed in nanoseconds 3624 drw 11a s l standard power low power * commercial only for low power 10ns (l10) speed grade. x g restricted hazardous substance device x die revistion blank first generation or current stepping being shipped ordering information
6.42 idt71v416s, IDT71V416L, 3.3v cmos static ram 4 meg (256k x 16-bit) commercial a nd industrial temperature ranges 9 corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 sramhelp@idt.com santa clara, ca 95054 fax: 408-492-8674 800-544-7726 www.idt.com the idt logo is a registered trademark of integrated device technology, inc. datasheet document history 08/5/99 updated to new format pg 6 revised footnote for t cw on write cycle no. 1 diagram 08/31/99 pg. 1?9 added industrial temperature range offering pg. 9 added datasheet document history 03/24/00 pg. 6 changed note to write cycle no. 1 according to footnotes 08/10/00 add 48 ball grid array package offering pg. 1 correct ttl to lvttl 09/11/ 02 pg. 2 updated tbd information for the 48 bga capacitance table 11/26/02 pg. 8 added "die revision" to ordering information 07/31/03 pg. 8 updated note, l10 speed grade commercial temperature only and updated die stepping from yf to y. 10/13/03 pg. 8 updated ordering information. refer to 71v416ys and 71v416yl datasheet for latest generation die step. 01/30/04 pg. 8 added "restricted hazardous substance device" to ordering information.
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